Once upon there was a request to modify the pcell of an nmos to make it more reliable against EOS. But the way we modified it by tinkering with the pcell RPO block layer distance to the gate to ballast the drain resistance. But by being too agressive we inadvertently created a device that susceptible to parasitic turn on. It would be called single transistor event turn on that would have the parasitic device turn on but wouldn’t stay latched which is different from the typical case of an SCR or typical parasitic latch up. For that it would be forever latched until you turn off the entire device disabling VCC. But in our case it would turn off as soon as you lowered VCC to a certain voltage in this case just 1 volt below the turn on. Turns out that it was a layout issue as well as a design issue. The mos device was way too large in terms of current sourcing for the application. To give context the mos device when turned on would source so much current in a small delta time that the inductance of the bond wire the drain was attached to would make the drain see a voltage about a few volts higher than normal. This higher voltage due to the high dv/dt on the inductance of the bondwire according to Faradays law would place a high electric field in the region of the large mos device. Due to the high electric field inside the device there occurred high impact ionization which is due to charge carriers being injected into the substrate due to the higher voltage event. And with charge carriers in an high electric field, there is then a force applied and the energy of the moving particles would get higher and higher as time passed.
I stole this paragraph below and I don’t feel shame about it.
Kinetic energy
KE = 0.5 • m • v2
where m = mass of object
v = speed of object
This is where I stopped stealing.
This is why its a good rule to have body ties. These catches these charge carriers before they can attain enough energy to cause an issue. And since the energy is based on the square of the velocity, Its like stopping an airplane early on the runway. If you wait and it gets faster and faster its going to do some damage when it runs into the the tower station head on.
Anyway, once these charges got enough energy they would start hitting other charge carriers which would create charge carrier pairs which is a precursor to avalanch breakdown can happen but anyway as more particles create more charge carrier pairs a current would start to form as this movement of carriers creates a current in the substrate, this creates a voltage due to the ohms law which turn on the parasitic npn since the voltage in the substrate is like putting a voltage on the base of an npn. So to make a long story short, put alot of body ties around large current devices or to be specific in between the every distance of 10 um or so. And kindly and respectfully let the designer your concern to make a driver mos that can source so much current in the delta time than you really need. Especially if the drain is tied to VCC which is tied to a bondwire. Maybe its ok if you tie the VCC to a bump pad but who knows. Why take a chance. Please let me know if I made a mistake somewhere in the logic. thanks. In hindsight quickly ask but don’t spend too much time since its not really your job to re-examine the design. Is this all necessarily to know for layout? Well if you want to solve problems then yes. Since CMOS is a planar technology which is a sea of PN junctions. And impact ionization as well augers recombination are needed to understand PN junction behavior. This can be used to solve latch issues or bias issues when you can’t figure out where the current is leaking from.